1. Field of the Invention
The present invention relates to a phase frequency detector and, more particularly, to a phase frequency detector (PFD), such as may be employed in a phase-locked loop (PLL), for example.
2. Background Information
FIG. 1 is a schematic diagram illustrating a conventional phase frequency detector to show the principle of operation. Likewise, FIG. 2 is a simplified schematic diagram illustrating a conventional phase-locked loop (PLL). The particular PLL illustrated is a charge pump PLL. Of course, a PFD may also be employed in a delay-locked loop (DLL) or in other circuits. As illustrated in FIG. 2, voltage-controlled oscillator (VCO) 220 produces a VCO output clock signal C2. VCO output clock signal C2 may be fed back directly or through a divider 280 if frequency multiplication is employed, although the following discussion assumes no divider. Phase frequency detector (PFD) 210 compares the phase and frequency of VCO clock signal C2 with the phase and frequency of reference clock signal C1. Based upon the phase delay between the two clock signals, phase frequency detector 210 produces an up signal and a down signal. These different signals are produced by different output ports. As illustrated in FIG. 2, these up and down signals are applied to control switches of a charge pump that will short circuit an electrical path including a current source, such as current sources 230 and 240. Thus, as illustrated in FIG. 2, when these switches close, current flows to charge or discharge capacitor 250. Therefore, depending upon the duration of the up signal and the down signal produced by phase frequency detector 210, the voltage on capacitor 250 is adjusted. Likewise, depending upon which switch(es) is (are) closed and the respective durations of the signals applied, the voltage across capacitor 250 may either increase or decrease. Furthermore, as illustrated in FIG. 2, capacitor 250 is coupled to voltage-controlled oscillator 220 so that the frequency of the output clock signal produced by VCO 220 will be adjusted in response to the voltage of capacitor 250. Therefore, a delay between VCO clock signal C2 and reference clock signal C1 should become smaller based, at least in part, upon the negative feedback operation of the PLL. When the output clock signal of VCO 220 closely matches reference clock signal C1 in phase and frequency, the PLL is xe2x80x9clockedxe2x80x9d.
FIG. 1 illustrates a conventional PFD. As illustrated in FIG. 1, this PFD includes two flip-flops 110 and 120 clocked by clock signals C1 and C2. As illustrated, each flip-flop includes a data port (xe2x80x9cDxe2x80x9d), a clock port (xe2x80x9cCKxe2x80x9d), and an output signal port (xe2x80x9cQxe2x80x9d). The two flip-flops are reset when both flip-flop output signal ports are active. This reset is accomplished by the output signal of AND gate 130. As is well-known, in the response curve of a PFD, a xe2x80x9cdead zonexe2x80x9d may occur around zero phase delay due to the limited ability of the PFD to produce, or circuits in the charge pump to respond to, relatively short up pulses or down pulses. For the PFD illustrated in FIG. 1 to avoid a dead zone, the reset path including AND gate 130 includes some delay allowing both flip-flop output signal ports to be active simultaneously for a short overlapping time.
Nonetheless, the PFD illustrated in FIG. 1 has some disadvantages. The delay in the reset path limits the speed of the PFD. Furthermore, the range of phase delays that the PFD is able to accommodate is limited by the reset delay. More specifically, the reset delay may result in the PFD missing a positive clock pulse edge transition as the magnitude of the phase delay between the two clock signals approaches a significant proportion of 360xc2x0. This missed positive clock pulse edge transition limits the range of phase delays the PFD is able to accommodate and, therefore, increases cycle slip and, hence, lock time of a PLL employing such a PFD. A need, therefore, exists for a PFD that addresses these problems.
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an up signal output port, and a down signal output port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up signal and a down signal based, at least in part, upon the magnitude of an amount of phase delay between two clock signals respectively applied to the PFD input ports.
Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an up signal output port, and a down signal output port. The PFD includes digital circuitry including transistors coupled in a configuration to produce a PFD output signal in which the sign of the phase delay indicated remains the sign of the phase delay between the applied clock signals even as the magnitude of the phase delay approaches a significant proportion of 360xc2x0.